Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Transformation-based high-level synthesis of fault-tolerant ASICs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A trace transformation technique for communication refinement
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
Reliability Properties Assessment at System Level: A Co-Design Framework
Journal of Electronic Testing: Theory and Applications
Faster and Simpler Algorithms for Multicommodity Flow and other Fractional Packing Problems.
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Reliability-Aware Co-Synthesis for Embedded Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Reliability-Centric High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
PISA: a platform and programming language independent interface for search algorithms
EMO'03 Proceedings of the 2nd international conference on Evolutionary multi-criterion optimization
Symbolic Reliability Analysis of Self-healing Networked Embedded Systems
SAFECOMP '08 Proceedings of the 27th international conference on Computer Safety, Reliability, and Security
Cross-Level compositional reliability analysis for embedded systems
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.00 |
In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems as well as wireless sensor networks. By introducing a model which is (1) suitable for heterogeneous networks with different communication bandwidths, (2) modeling of routing restrictions, and (3) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. Due to the often error-prone communication in networks, we allow for routing each data dependency over multiple routes in the networks. With this strategy, our methodology is able to increase the reliability of the entire system. This reliability analysis is based on Binary Decision Diagrams (BDDs) and is integrated in our multi-objective design space exploration. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach.