Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Reliability prediction for component-based software architectures
Journal of Systems and Software - Special issue on: Software architecture - Engineering quality attributes
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Reliability-Centric High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design space exploration of reliable networked embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Reliable multiprocessor system-on-chip synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Reliability-aware Co-synthesis for Embedded Systems
Journal of VLSI Signal Processing Systems
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
Synthesis of fault-tolerant embedded systems
Proceedings of the conference on Design, automation and test in Europe
Application-specific MPSoC reliability optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ESL power analysis of embedded processors for temperature and reliability estimations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Reliability limits for the gate insulator in CMOS technology
IBM Journal of Research and Development
System-level reliability modeling for MPSoCs
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Opt4J: a modular framework for meta-heuristic optimization
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Symbolic system level reliability analysis
Proceedings of the International Conference on Computer-Aided Design
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Ever shrinking device structures are one of the main reasons for a growing inherent unreliability of embedded system components. As a remedy, various means to increase the reliability of complex embedded systems at several levels of abstraction are available. In fact, their efficient application is a key factor for the successful design of reliable embedded systems. While analysis approaches that evaluate these techniques and their advantages and disadvantages at particular levels exist, an overall system analysis that has to work cross-level is still lacking. This paper introduces a framework for cross-level reliability analysis that enables a seamless and flexible combination of various reliability analysis techniques across different levels of abstraction. For this purpose, a proposed framework provides mechanisms for (a) the composition and decomposition of the system during analysis and (b) the connection of different levels of abstraction by adapters that convert and abstract analysis results. As a case-study, the framework extends and combines three analysis approaches from the MPSoC domain: (I) a BDD-based reliability analysis considers redundancies in the system structure, (II) an analytical behavioral model to consider computational activity, and (III) a temperature simulator for processor cores. This enables to capture thermal reliability threats at transistor level in an overall system analysis. The approach is seamlessly integrated in an automatic Electronic System Level (ESL) tool flow.