Scheduling algorithms for fault-tolerance in hard-real-time systems
Real-Time Systems - Special issue on responsive computer systems
IEEE Transactions on Computers
Tolerance to Multiple Transient Faults for Aperiodic Tasks in Hard Real-Time Systems
IEEE Transactions on Computers
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Scheduling of conditional process graphs for the synthesis of embedded systems
Proceedings of the conference on Design, automation and test in Europe
Analysis of Checkpointing for Real-Time Systems
Real-Time Systems
Fault-Tolerant Real-Time Systems: The Problem of Replica Determinism
Fault-Tolerant Real-Time Systems: The Problem of Replica Determinism
A survey of rollback-recovery protocols in message-passing systems
ACM Computing Surveys (CSUR)
A Fault-Tolerant Scheduling Algorithm for Real-Time Periodic Tasks with Possible Software Faults
IEEE Transactions on Computers
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Roll-forward error recovery in embedded real-time systems
ICPADS '96 Proceedings of the 1996 International Conference on Parallel and Distributed Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Reliability-Aware Co-Synthesis for Embedded Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Scheduling of fault-tolerant embedded systems with soft and hard timing constraints
Proceedings of the conference on Design, automation and test in Europe
Transparent recovery from intermittent faults in time-triggered distributed systems
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Exploiting data-redundancy in reliability-aware networked embedded system design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Cost-effective safety and fault localization using distributed temporal redundancy
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Cross-Level compositional reliability analysis for embedded systems
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
ACM Transactions on Embedded Computing Systems (TECS)
DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors
Microprocessors & Microsystems
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This work addresses the issue of design optimization for fault-tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.