The consensus problem in fault-tolerant computing
ACM Computing Surveys (CSUR)
List scheduling with and without communication delays
Parallel Computing
Implementing Fail-Silent Nodes for Distributed Systems
IEEE Transactions on Computers
Reaching strong consensus in the presence of mixed failure types
Information Sciences—Informatics and Computer Science: An International Journal
The Byzantine Generals Problem
ACM Transactions on Programming Languages and Systems (TOPLAS)
Embedded Control Systems Development with Giotto
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Dependability: Basic Concepts and Terminology
Dependability: Basic Concepts and Terminology
What's Ahead for Embedded Software?
Computer
Fault-Tolerant Scheduling on a Hard Real-Time Multiprocessor System
Proceedings of the 8th International Symposium on Parallel Processing
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
The Transparent Implementation of Fault Tolerance in the Time-Triggered Architecture
DCCA '99 Proceedings of the conference on Dependable Computing for Critical Applications
Byzantine clock synchronization
PODC '84 Proceedings of the third annual ACM symposium on Principles of distributed computing
Fault-Tolerant Real-Time Scheduling using Passive Replicas
PRFTS '97 Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems
Real-Time Scheduling in a Generic Fault-Tolerant Architecture
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Fault-tolerant platforms for automotive safety-critical applications
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Computing optimal self-repair actions: damage minimization versus repair time
WADS '05 Proceedings of the 2005 workshop on Architecting dependable systems
A formal approach to fault tree synthesis for the analysis of distributed fault tolerant systems
Proceedings of the 5th ACM international conference on Embedded software
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe
Virtual platforms and timing analysis: status, challenges and future directions
Proceedings of the 44th annual Design Automation Conference
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Logical reliability of interacting real-time tasks
Proceedings of the conference on Design, automation and test in Europe
Scheduling of fault-tolerant embedded systems with soft and hard timing constraints
Proceedings of the conference on Design, automation and test in Europe
Synthesis of fault-tolerant embedded systems
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Towards fault-tolerant embedded systems with imperfect fault detection
Proceedings of the 49th Annual Design Automation Conference
ACM Transactions on Embedded Computing Systems (TECS)
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Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of the cost/coverage trade-offs of fault-tolerant solutions. This further complicates the difficult task of deploying the embedded software that implements the control algorithms on the execution platform that is often distributed around the plant (as it is typical, for instance, in automotive applications). We propose a synthesis-based design methodology that relieves the designers from the burden of specifying detailed mechanisms for addressing platform faults, while involving them in the definition of the overall fault-tolerance strategy. Thus, they can focus on addressing plant faults within their control algorithms, selecting the best components for the execution platform, and de.ning an accurate fault model. Our approach is centered on a new model of computation, Fault Tolerant Data Flows (FTDF), that enables the integration of formal validation techniques.