A formal approach to fault tree synthesis for the analysis of distributed fault tolerant systems

Authors:
Mark L. McKelvin, Jr.;Gabriel Eirea;Claudio Pinello;Sri Kanajan;Alberto L. Sangiovanni-Vincentelli
Affiliations:
University of California - Berkeley, Berkeley, CA;University of California - Berkeley, Berkeley, CA;General Motors Berkeley Lab, Berkeley, CA;General Motors Berkeley Lab, Berkeley, CA;University of California - Berkeley, Berkeley, CA
Venue:
Proceedings of the 5th ACM international conference on Embedded software
Year:
2005

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Abstract

Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of both performance versus cost aspects and fault coverage of fault tolerant solutions. This further complicates the difficult task of deploying the embedded software that implements the control algorithms on a possibly distributed execution platform (for instance in automotive applications). In this paper, we present a novel technique for constructing a fault tree that models how component faults may lead to system failure. The fault tree enables us to use existing commercial analysis tools to assess a number of dependability metrics of the system. Our approach is centered on a model of computation, Fault Tolerant Data Flow (FTDF), that enables the integration of formal verification techniques. This new analysis capability is added to an existing design framework, also based on FTDF, that enables a synthesis-based, correct-by-construction, design methodology for the deployment of real-time feedback control systems in safety critical applications.