Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Scheduling algorithms for fault-tolerance in hard-real-time systems
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Proceedings of the Conference on Design, Automation and Test in Europe
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ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Journal of Parallel and Distributed Computing
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ACM Computing Surveys (CSUR)
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. Addressing simultaneously energy and reliability is especially challenging because lowering the voltage to reduce the energy consumption has been shown to increase the transient fault rates. In addition, time-redundancy based fault-tolerance techniques such as re-execution and dynamic voltage scaling-based low-power techniques are competing for the slack in the schedules. Our approach decides the voltage levels and start times of processes and the transmission times of messages, such that the transient faults are tolerated, the timing constraints of the application are satisfied and the energy is minimized. We present a constraint logic programming-based approach which is able to find reliable and schedulable implementations within limited energy and hardware resources.