FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection

Authors:
John Conner;Yuan Xie;Mahmut Kandemir;Robert Dick;Greg Link
Affiliations:
The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;Northwestern University;The Pennsylvania State University
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 5
Cited 3

TGFF: task graphs for free

Proceedings of the 6th international workshop on Hardware/software codesign
Genetic Algorithms in Search, Optimization and Machine Learning

Genetic Algorithms in Search, Optimization and Machine Learning
Hardware/Software CO-Design: Principles and Practice

Hardware/Software CO-Design: Principles and Practice
Cosynthesis of multiprocessor architectures with high availability

VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Reliability-Aware Co-Synthesis for Embedded Systems

ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference

Synthesis of fault-tolerant embedded systems

Proceedings of the conference on Design, automation and test in Europe
Design optimization of time-and cost-constrained fault-tolerant embedded systems with checkpointing and replication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling and Optimization of Fault-Tolerant Embedded Systems with Transparency/Performance Trade-Offs

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Embedded real-time systems are becoming increasingly complex. To combat the rising design cost of those systems, co-synthesis tools that map tasks to systems containing both software and specialized hardware have been developed. As system transient fault rates increase due to technology scaling, embedded systems must be designed in fault tolerant ways to maintain system reliability. This paper presents and analyzes FD-HGAC, a tool using a genetic algorithm and heuristics to design real-time systems with partial fault detection. Results of numerous trials of the tool are shown to produce systems with average 22% detection coverage that incurs no cost or performance penalty.