Modeling concurrency with partial orders
International Journal of Parallel Programming
Proceedings of the LITP spring school on theoretical computer science on Semantics of systems of concurrent processes
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Communication refinement in video systems on chip
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Action Systems and Action Refinement in the Development of Parallel Systems - An Algebraic Approach
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
An object-oriented design process for system-on-chip using UML
Proceedings of the 15th international symposium on System Synthesis
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Towards efficient design space exploration of heterogeneous embedded media systems
Embedded processor design challenges
An IDF-based trace transformation method for communication refinement
Proceedings of the 40th annual Design Automation Conference
SystemC
Retargetable profiling for rapid, early system-level design space exploration
Proceedings of the 41st annual Design Automation Conference
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
Multi-metric and multi-entity characterization of applications for early system design exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Design space exploration of reliable networked embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
A SystemC-based design methodology for digital signal processing systems
EURASIP Journal on Embedded Systems
UMTS MPSoC design evaluation using a system level design framework
Proceedings of the Conference on Design, Automation and Test in Europe
A case for visualization-integrated system-level design space exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
RCML: An Environment for Estimation Modeling of Reconfigurable Computing Systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
| Hi-index | 0.00 |
Models of computation like Kahn and dataflow process networks provide convenient means for modeling signal processing applications. This is partly due to the abstract primitives that these models offer for communication between concurrent processes. However, when mapping an application model onto an architecture, these primitives need to be mapped onto architecture level communication primitives. We present a trace transformation technique that supports a system architect in performing this communication refinement. We discuss the implementation of this technique in a tool for architecture exploration named SPADE and present examples.