Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A trace transformation technique for communication refinement
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
FPGA architecture characterization for system level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Source-level timing annotation and simulation for a heterogeneous multiprocessor
Proceedings of the conference on Design, automation and test in Europe
System modeling and transformational design refinement in ForSyDe [formal system design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design synthesis and optimization for automotive embedded systems
Proceedings of the 2014 on International symposium on physical design
A Case Study of Simulation and Performance Evaluationof a SDR Baseband Architecture
Journal of Signal Processing Systems
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Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design framework, Metro II, to carry out simulation and design space exploration of multi-core architectures. We illustrate the design methodology on a UMTS data link layer design case study with both a timed and untimed functional model as well as a complete set of MPSoC architectural services. We compare different architectures (including RTOSes) explored with Metro II and quantify the associated simulation overhead.