Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
A Hardware-Software Real-Time Operating System Framework for SoCs
IEEE Design & Test
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Proceedings of the 40th annual Design Automation Conference
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Context-Aware Performance Analysis for Efficient Embedded System Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Unified Component Integration Flow for Multi-Processor SoC Design and Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Task-accurate performance modeling in SystemC for real-time multi-processor architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A SystemC-based design methodology for digital signal processing systems
EURASIP Journal on Embedded Systems
A fast and generic hybrid simulation approach using C virtual machine
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Interrupt modeling for efficient high-level scheduler design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data locality enhancement for CMPs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Integration, the VLSI Journal
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
High-Level System Modeling for Rapid HW/SW Architecture Exploration
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Exposing non-standard architectures to embedded software using compile-time virtualisation
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Dynamic thread and data mapping for NoC based CMPs
Proceedings of the 46th Annual Design Automation Conference
Fast and accurate processor models for efficient MPSoC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An ILP formulation for task mapping and scheduling on multi-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
UMTS MPSoC design evaluation using a system level design framework
Proceedings of the Conference on Design, Automation and Test in Europe
Dimensioning heterogeneous MPSoCs via parallelism analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Analog Integrated Circuits and Signal Processing
Neighborhood-aware data locality optimization for NoC-based multicores
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
A compiler infrastructure for embedded heterogeneous MPSoCs
Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores
On confident task-accurate performance estimation
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
On robust task-accurate performance estimation
Proceedings of the 50th Annual Design Automation Conference
Virtual platforms: breaking new grounds
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Multi-core system performance prediction and analysis at the ESL
International Journal of Computational Science and Engineering
A compiler infrastructure for embedded heterogeneous MPSoCs
Parallel Computing
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Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by demanding signal processing and networking applications. However, in order to take advantage of the available processing and communication resources, an optimal mapping of the application tasks onto the platform resources is of crucial importance. In this paper, we propose a SystemC-based simulation framework, which enables the quantitative evaluation of application-to-platform mappings by means of an executable performance model. Key element of our approach is a configurable event-driven Virtual Processing Unit to capture the timing behavior of multi-processor/multi-threaded MP-SoC platforms. The framework features an XML-based declarative construction mechanism of the performance model to significantly accelerate the navigation in large design spaces. The capabilities of the proposed framework in terms of design space exploration is presented by a case study of a commercially available MP-SoC platform for networking applications. Focussing on the application to architecture mapping, our introduced framework highlights the potential for optimization of an efficient design space exploration environment.