The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Characterizations of parallelism in applications and their use in scheduling
SIGMETRICS '89 Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Proceedings of the 6th international workshop on Hardware/software codesign
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
IEEE Transactions on Parallel and Distributed Systems
A multiobjective optimization model for exploring multiprocessor mappings of process networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
A mapping framework for guided design space exploration of heterogeneous MP-SoCs
Proceedings of the conference on Design, automation and test in Europe
A Real-Time Programming Model for Heterogeneous MPSoCs
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Code generation for STA architecture
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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In embedded computing we face a continuously growing algorithm complexity combined with a constantly rising number of applications running on a single system. Multi-core systems are becoming popular to cope with these requirements. Growing computational complexity is handled by increasing the number of cores and core types within one system - leading to heterogeneous many-core MPSoCs in the near future. One key challenge in designing such systems is to determine the number of cores required to meet performance, power and area constraints. In this paper we present a methodology that helps dimensioning these systems via a novel parallelism analysis methodology within seconds. The presented methodology has an average performance estimation error of less than 4% compared to transaction level simulation.