&mgr;C/OS: the real-time kernel
&mgr;C/OS: the real-time kernel
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DynamoSim: a trace-based dynamically compiled instruction set simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multi-metric and multi-entity characterization of applications for early system design exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Multiprocessor performance estimation using hybrid simulation
Proceedings of the 45th annual Design Automation Conference
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
HdSC: a fast and preemptive modeling for on host HdS development
Proceedings of the 24th symposium on Integrated circuits and systems design
Support for early verification of embedded real-time systems through UML models simulation
ACM SIGOPS Operating Systems Review
Synchronization for hybrid MPSoC full-system simulation
Proceedings of the 49th Annual Design Automation Conference
Automated, retargetable back-annotation for host compiled performance and power modeling
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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With growing system complexity and ever-increasing software content, the development of embedded software for upcoming MPSoC architectures is a tremendous challenge. Traditional ISS-based validation becomes infeasible due to the large complexity. Addressing the need for flexible and fast simulating models, we introduce in this article our approach of abstract processor modeling in the context of multiprocessor architectures. We combine modeling of computation on processors with an abstract RTOS and accurate interrupt handling into a versatile, multifaceted processor model with several levels of features. Our processor models are utilized in a framework allowing designers to develop a system in a top-down manner using automatic model generation and compilation down to a given MPSoC architecture. During generation, instances of our processor models are integrated into a system model combining software, hardware, and bus communication. The generated system model serves for rapid design space exploration and a fast and accurate system validation. Our experimental results show the benefits of our processor modeling using an actual multiprocessor mobile phone baseband platform. Our abstract models of this complex system reach a simulation speed of 300MCycles/s within a high accuracy of less than 3% error. In addition, our results quantify the speed/accuracy trade-off at varying abstraction levels of our models to guide future processor model designers.