Support for early verification of embedded real-time systems through UML models simulation

  • Authors:
  • Marco A. Wehrmeister;Joao G. Packer;Luis M. Ceron

  • Affiliations:
  • Santa Catarina State University, Joinville, Brazil;Santa Catarina State University, Joinville, Brazil;Santa Catarina State University, Joinville, Brazil

  • Venue:
  • ACM SIGOPS Operating Systems Review
  • Year:
  • 2012

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Abstract

Identifying errors in early design phases leads to a decrease in the repairing cost compared to the situation in which such problems are discovered only in advanced design phases. This work is a first step toward an automatic verification approach for embedded and real-time systems' high-level specifications, such as UML models. This paper presents a model-driven framework to simulate system's behavior already in early design phases, prior to the implementation phase. More specifically, the mentioned framework simulates the behavior specified within UML models, generating a trace of executed actions for the selected behaviors. The achieved results show that early simulation of UML models is practicable, opening room for its usage in different CASE tools for early verification and validation of embedded and real-time systems.