Abstract, Multifaceted Modeling of Embedded Processors for System Level Design

  • Authors:

  • Gunar Schirner;Andreas Gerstlauer;Rainer Domer

  • Affiliations:

  • Center for Embedded Computer Systems, University of California, Irvine, USA. hschirne@cecs.uci.edu;Center for Embedded Computer Systems, University of California, Irvine, USA. gerstl@cecs.uci.edu;Center for Embedded Computer Systems, University of California, Irvine, USA. doemer@cecs.uci.edu

  • Venue:
  • ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
  • Year:
  • 2007

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Abstract

Embedded software is playing an increasing role in todays SoC designs. It allows a flexible adaptation to evolving standards and to customer specific demands. As software emerges more and more as a design bottleneck, early, fast, and accurate simulation of software becomes crucial. Therefore, an efficient modeling of programmable processors at high levels of abstraction is required. In this article, we focus on abstraction of computation and describe our abstract modeling of embedded processors. We combine the computation modeling with task scheduling support and accurate interrupt handling into a versatile, multi-faceted processor model with varying levels of features. Incorporating the abstract processor model into a communication model, we achieve fast co-simulation of a complete custom target architecture for a system level design exploration. We demonstrate the effectiveness of our approach using an industrial strength telecommunication example executing on a Motorola DSP architecture. Our results indicate the tremendous value of abstract processor modeling. Different feature levels achieve a simulation speedup of up to 6600 times with an error of less than 8% over a ISS based simulation. On the other hand, our full featured model exhibits a 3% error in simulated timing with a 1800 times speedup.