Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the Optimal Variable Ordering for Binary Decision Diagrams
IEEE Transactions on Computers
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Two-level logic minimization: an overview
Integration, the VLSI Journal
Series-parallel functions and FPGA logic module design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Algorithm for Total Symmetric OBDD Detection
IEEE Transactions on Computers
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
Solving Boolean Equations Using ROSOP Forms
IEEE Transactions on Computers
Fast exact minimization of BDDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Fast functional evaluation of candidate OBDD variable orderings
EURO-DAC '91 Proceedings of the conference on European design automation
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
On designing universal logic blocks and their application to FPGA design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 14.98 |
In this paper, we analyze the basic properties of some Boolean function classes and propose a low complexity OBDD variable ordering algorithm, which is exact (optimum) to some classes of functions and very effective to general two-level form functions. We show that the class of series-parallel functions, which can be expressed by a factored form where each variable appears exactly once, can yield exact OBDD variable orderings in polynomial time. We also study the thin Boolean functions whose corresponding OBDDs can be represented by the form of thin OBDDs in which the number of nonterminal nodes is equal to the number of input variables. We show that a thin Boolean function always has an essential prime cube cover and the class of series-parallel functions is a proper subset of thin Boolean functions. We propose a heuristic viewing OBDDs as evaluation machines with function cube covers as their inputs and apply a queuing principle in the algorithm design. Our heuristic, the augmented Dynamic Shortest Cube First algorithm, is proven to be optimum for the series-parallel functions and also be very effective for general two-level form functions. Experimental results on a large number of two-level form benchmark circuits show that the algorithm yields an OBDD total size reduction of over 51 percent with only 7 percent CPU time compared to the well-known network-based Fan-In Heuristic implemented in the SIS package. Comparing to the known exact results, ours is only 49 percent larger in size while only uses 0.001 percent CPU time.