Using Decision Diagrams to Design ULMs for FPGAs
IEEE Transactions on Computers
OBDD Minimization Based on Two-Level Representation of Boolean Functions
IEEE Transactions on Computers
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
Physical design methodologies for performance predictability and manufacturability
Proceedings of the 1st conference on Computing frontiers
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
A tool for analysis of universal logic gates functionality
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a general methodology to determine the logic function of a programmable cell. It is based on the concept of universal logic gate (ULG) that is capable of being configured to a given set of functions. The cells studied here can be configured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. One application of this technique is to select an appropriate programmable cell structure for FPGA architecture. The Actel 2 and the three-input look-up table cells are studied and compared to the cell that has been designed using the approach described here. Experimental results suggest that the new cell behaves as well as the Actel 2 cell in terms of logic power, but requires substantially less area and wiring overhead