Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Functional approaches to generating orderings for efficient symbolic representations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Path-delay-fault testability properties of multiplexor-based networks
Integration, the VLSI Journal
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Free MDD-based software optimization techniques for embedded systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
OBDD Minimization Based on Two-Level Representation of Boolean Functions
IEEE Transactions on Computers
The nonapproximability of OBDD minimization
Information and Computation
Ordered binary decision diagrams as knowledge-bases
Artificial Intelligence
Sample Method for Minimization of OBDDs
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Learning to order BDD variables in verification
Journal of Artificial Intelligence Research
Computing argumentation in polynomial number of BDD operations: a preliminary report
ArgMAS'10 Proceedings of the 7th international conference on Argumentation in Multi-Agent Systems
International Journal of Cognitive Informatics and Natural Intelligence
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We present a new exact algorithm for finding the optimal variable or deringfor r educ edordered Binary Decision Diagrams (BDDs). The algorithm makes use of a lower bound technique known from VLSI design.Up to now this technique has been use donly for the oreticalconsider ationsand it is adapte dhere for our purp ose. Furthermore, the algorithm supports symmetry aspects and makes use of a hashing b aseddata structure. Exp erimental esults are given to demonstrate the efficiency of our appr oach. We succeeded in minimizing adder functions with up to 64 variables, while all other pr eviously pr esente d appr oaches fail.