Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multilevel logic synthesis for arithmetic functions
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fast exact minimization of BDDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
OKFDD minimization by genetic algorithms with application to circuit design
Integration, the VLSI Journal
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wave steering to integrate logic and physical syntheses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
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The introduction of Decision Diagrams (DDs) has brought new means towards solving many of the problems involved in digital circuit design. Compactness of the representation is one key issue. Ordered Pseudo Kronecker Decision Diagrams (OPKDDs) together with the use of complemented edges is known to offer the most general ordered, read-once DD representation at the bit-level, hence OPKDDs hold all minimal sized bit-level ordered DDs for a given function. This representation allows us to trade-off diagram canonicity against compactness. Ternary-OPKDDs (TOPKDDs) implicitly holds all OPKDDs for a given variable order. We state the canonicity criteria for TOPKDDs having complemented edges and develop an efficient sifting based method for their minimization. Furthermore, a heuristic minimization algorithm for OPKDDs is devised, utilizing the redundancies of Ternary-OPKDDs (TOPKDDs). Experiments on a set of MCNC benchmarks confirm the potential compactness of OPKDDs and demonstrate the efficiency of the proposed heuristics.