Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Valid clock frequencies and their computation in wavepipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pipelining Sequential Circuits with Wave Steering
IEEE Transactions on Computers
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Wave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.