Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Proceedings of the 37th Annual Design Automation Conference
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Signal representation guided synthesis using carry-save adders for synchronous data-path circuits
Proceedings of the 38th annual Design Automation Conference
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
Self-referential verification of gate-level implementations of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Wave steering to integrate logic and physical syntheses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Optimizing high speed arithmetic circuits using three-term extraction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths
Integration, the VLSI Journal
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Carry-save-adder(CSA) is one of the most widely used schemes for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs. Specifically, we present a polynomial time algorithm which finds an optimal-timing CSA allocation for a given arithmetic expression. In addition, we extend our result for CSA allocation to the problem of optimizing arithmetic expressions across the boundary of design hierarchy by introducing a new concept, called auxiliary ports. Our algorithm can be used to carry out the CSA allocation step optimally and automatically, and this can be done within the context of a standard HDL synthesis environment.