Using C to write portable CMOS VLSI module generators
EURO-DAC '94 Proceedings of the conference on European design automation
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
MyHDL: a python-based hardware description language
Linux Journal
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Some Optimizations of Hardware Multiplication by Constant Matrices
IEEE Transactions on Computers
Towards the automatic exploration of arithmetic-circuit architectures
Proceedings of the 43rd annual Design Automation Conference
Arithmetic Data Path Optimization Using Borrow-Save Representation
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Datapath Synthesis for Standard-Cell Design
ARITH '09 Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic
Modified Booth algorithm for high radix fixed-point multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The rapid pace of technological evolution places a substantial amount of pressure on minimizing the time-to-market for integrated circuit designers. Such pressure on the design cycle combined with strict performance constraints makes the use of computer-aided design tools mandatory. In this context, CAD tools that improve performance in terms of delay, area or power consumption are of interest. In this paper, we present a design environment that is dedicated to arithmetic datapath design support. This environment consists of the following elements: (1) Stratus: a language that is dedicated to the parameterized generation of VLSI modules and that allows several levels of abstraction; (2) ArithLib: a library of parameterized arithmetic IP-block generators; and (3) several optimization algorithms that choose the best architecture for each arithmetic operator of a datapath, given an optimization goal. These algorithms consider binary arithmetic as well as redundant arithmetic, given the good intrinsic performance of redundant architectures. In addition, experimental results are presented.