High-level algorithm and architecture transformations for DSP synthesis
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Maximally fast and arbitrarily fast implementation of linear computations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Circuit optimization using carry-save-adder cells
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths
Integration, the VLSI Journal
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Timing and area of circuits are two of the most important design criteria to be optimized in data path synthesis. In addition, carry-save-adder (CSA) has been proven to be one of the most efficient implementation units in optimizing timing and/or area of arithmetic circuits. However, the existing approaches are restricted in using CSAs, i.e., optimizing operation trees separately without any interaction between them, resulting in a locally optimized CSA circuit. To overcome this limitation, we propose a practically efficient solution to the problem of an accurate exploration of timing and area trade-offs in optimizing arithmetic circuits in the presence of multiple operation trees using CSAs. The application of our approach is able to find a best CSA implementation of circuit in terms of timing and area.