Multiplication by Integer constants
Software—Practice & Experience
Integer Multiplication and Division on the HP Precision Architecture
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Theory and Applications of the Double-Base Number System
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DCT Implementation with Distributed Arithmetic
IEEE Transactions on Computers
Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
Some Optimizations of Hardware Multiplication by Constant Matrices
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Multiplier-free realizations for FIR multirate converters based onmixed-radix number representation
IEEE Transactions on Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computers
A generalization of a fast RNS conversion for a new 4-modulus base
IEEE Transactions on Circuits and Systems II: Express Briefs
High-performance hardware operators for polynomial evaluation
International Journal of High Performance Systems Architecture
Optimizing energy to minimize errors in dataflow graphs using approximate adders
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Optimization Algorithms for the Multiplierless Realization of Linear Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimisation of constant matrix multiplication operation hardware using a genetic algorithm
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths
Integration, the VLSI Journal
Hi-index | 14.98 |
This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.