DCT Implementation with Distributed Arithmetic

Authors:
Sungwook Yu;Earl E. Swartzlander, Jr.
Affiliations:
Intel Corp., Austin, TX;Univ. of Texas, Austin
Venue:
IEEE Transactions on Computers
Year:
2001

Citing 1
Cited 13

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Novel VLSI algorithm and architecture with good quantization properties for a high-throughput area efficient systolic array implementation of DCT

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High throughput DA-based DCT with high accuracy error-compensated adder tree

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On reconfiguration-oriented approximate adder design and its application

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Abstract

This paper presents an efficient method for implementing the Discrete Cosine Transform (DCT) with distributed arithmetic. While conventional approaches use the original DCT algorithm or the even-odd frequency decomposition of the DCT algorithm, the proposed architecture uses the recursive DCT algorithm and requires less area than the conventional approaches, regardless of the memory reduction techniques employed in the ROM Accumulators (RACs). An efficient architecture for implementing the scaled DCT with distributed arithmetic is also proposed. The new architecture requires even less area while keeping the same structural regularity for an easy VLSI implementation. A comparison of synthesized DCT processors shows that the proposed method reduces the hardware area of regular and scaled DCT processors by 17 percent and 23 percent, respectively, relative to a conventional design. With the row-column decomposition method, the proposed architectures can be easily extended to compute the two-dimensional DCT required in many image compression applications such as HDTV.