Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Total System Energy Minimization for Wireless Image Transmission
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
DCT Implementation with Distributed Arithmetic
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NEDA: a low-power high-performance DCT architecture
IEEE Transactions on Signal Processing
FPGA implementation of a novel DCT architecture reducing constant cosine terms
ACM SIGARCH Computer Architecture News
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In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.