Computer Architecture and Organization
Computer Architecture and Organization
A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption
Journal of Signal Processing Systems
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This paper presents a new scalable architecture for Discrete Cosine Transform (DCT). In contrast to the conventional DCT architecture, the proposed architecture reduces the number of constant cosine terms using the matrix transposition and symmetry property. This in turn, considerably reduces the computation time. The architecture is scalable and it can be extended to support any transform length. The architecture was validated on Xilinx Vertex-4 FPGA.