Novel VLSI algorithm and architecture with good quantization properties for a high-throughput area efficient systolic array implementation of DCT

  • Authors:

  • Doru Florin Chiper;Paul Ungureanu

  • Affiliations:

  • Faculty of Electronics, Telecommunications and Information Technology, Technical University "Gh. Asachi", Iasi, Romania;Faculty of Electronics, Telecommunications and Information Technology, Technical University "Gh. Asachi", Iasi, Romania

  • Venue:
  • EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
  • Year:
  • 2011

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Abstract

Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The proposed restructuring technique transforms the DCT algorithm into a cycle-convolution and a pseudo-cycle convolution structure as basic computational forms. The proposed solution has been specially designed to have good fixed-point error performances that have been exploited to further reduce the hardware complexity and power consumption. It leads to a ROM based VLSI kernel with good quantization properties. A parallel VLSI algorithm and architecture with a good fixed point implementation appropriate for a memory-based implementation have been obtained. The proposed algorithm can bemapped onto two linear systolic arrays with similar length and form. They can be further efficientlymerged into a single array using an appropriate hardware sharing technique. A highly efficient VLSI chip can be thus obtained with appealing features as good architectural topology, processing speed, hardware complexity and I/O costs. Moreover, the proposed solution substantially reduces the hardware overhead involved by the pre-processing stage that for short length DCT consumes an important percentage of the chip area.