Unified systolic arrays for computation of the DCT/DST/DHT

Authors:
Sung Bum Pan;Rae-Hong Park
Affiliations:
Dept. of Electron. Eng., Sogang Univ., Seoul;-
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
1997

Citing 0
Cited 4

A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms

IEEE Transactions on Computers
Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec

Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Novel VLSI algorithm and architecture with good quantization properties for a high-throughput area efficient systolic array implementation of DCT

EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
Area-Time efficient systolic architecture for the DCT

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

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Abstract

We propose unified systolic arrays for computation of the one-dimensional (1-D) and two-dimensional (2-D) discrete cosine transform/discrete sine transform/discrete Hartley transform (DCT/DST/DHT). By decomposing the transforms into even- and odd-numbered frequency samples, the proposed architecture computes the 1-D DCT/DST/DHT. Compared to the conventional methods, the proposed systolic arrays exhibit advantages in terms of the number of PE's and latency. We generalize the proposed structure for computation of the 2-D DCT/DST/DHT. The unified systolic arrays can be employed for computation of the inverse DCT/DST/DHT (IDCT/IDST/IDHT)