Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic

Authors:
Soumik Ghosh;Soujanya Venigalla;Magdy Bayoumi
Affiliations:
University of Louisiana at Lafayette;University of Louisiana at Lafayette;University of Louisiana at Lafayette
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

Citing 5
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Abstract

The paper describes the design and implementation of an 8脳8 2D DCT chip for use in low-power applications. The design exploits a Coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8脳8 2D DCT @ 50 MHz consuming around 137mW of power.