Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Optimisation techniques for the system on chip implementation of JPEG encoder
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
ESVD: an integrated energy scalable framework for low-power video decoding systems
EURASIP Journal on Wireless Communications and Networking - Special issue on multimedia communications over next generation wireless networks
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms
Proceedings of the 24th symposium on Integrated circuits and systems design
Power-efficient video encoding on resource-limited systems: A game-theoretic approach
Future Generation Computer Systems
VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
International Journal of Circuit Theory and Applications
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This paper examines low power design techniques for discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuits applicable for low bit rate wireless video systems. The techniques include skipping DCT computation of low energy macroblocks, skipping IDCT computation of blocks with all coefficients equal to zero, using lower precision constant multipliers, gating the clock, and reducing transitions in the data path. The proposed DCT and IDCT circuits reduce power dissipation by, on average, 94% over baseline reference circuits.