Encyclopedia of graphics file formats (2nd ed.)
Encyclopedia of graphics file formats (2nd ed.)
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
Integration, the VLSI Journal
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
Microprocessors & Microsystems
IEEE Transactions on Computers
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
Low power design of DCT and IDCT for low bit rate video codecs
IEEE Transactions on Multimedia
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties
IEEE Transactions on Circuits and Systems for Video Technology
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The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents an energy-efficient FDCT/IDCT configurable IP core. Synthesis for 90 nm resulted in 50 MHz as maximum frequency and 1.66 mW as total power, achieving a throughput of 188.2 Mpixels/s, which is enough to process two HDTV@1080p videos in real time. The IP core architecture is based on Massimino's algorithm, which was chosen for its accuracy and parallelism. The exploration of its parallelism resulted in a fully-combinational 1-D FDCT/IDCT configurable datapath. In addition, the IP core is IEEE-1180 compliant. Comparisons with related work, in terms of energy efficiency (mJ/Mpixel), revealed that our architecture is at least 64% more efficient than other DCT architectures.