Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Digital Video and HDTV Algorithms and Interfaces
Digital Video and HDTV Algorithms and Interfaces
Fast algorithms for the discrete cosine transform
IEEE Transactions on Signal Processing
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
IEEE Transactions on Circuits and Systems for Video Technology
An entropy coding system for digital HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
Transforms and quantization design targeting the H.264/AVC intra prediction constraints
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
An iterative logarithmic multiplier
Microprocessors & Microsystems
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms
Proceedings of the 24th symposium on Integrated circuits and systems design
Low power hardware-based image compression solution for wireless camera sensor networks
Computer Standards & Interfaces
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This paper presents the design of a soft IP for JPEG compression targeted for high performance in a FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The JPEG compressor architecture was designed in a hierarchical and modular fashion and the details of the global architecture and of its modules are presented in this paper. A modular and strictly structural VHDL design is followed to develop the JPEG compressor soft IP. The VHDL codes were synthesized to Altera and Xilinx FPGAs. Synthesis results and relevant performance comparisons with related works are presented. Our high throughput compressor is able to compress 39.8 millions of pixels per second when mapped onto an Altera FLEX 10KE FPGA. Our JPEG soft IP mapped to FLEX 10KE low cost FPGA is able to compress 115 images per second in SDTV resolution (720x480 pixels). Considering this SDTV resolution our design is worthy as a core of an M-JPEG video compressor, reaching a real time processing rate of 30fps, once mapped to the FLEX 10KE FPGA device.