Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
Microprocessors & Microsystems
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Efficient hardware solution for practical intra h.264/SVC video encoder implementation
Proceedings of the 24th symposium on Integrated circuits and systems design
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This paper presents an architecture for a dedicated transforms and quantization loop targeting the Intra Prediction of the H.264/AVC video coding standard. The transforms and quantization loop is a bottleneck for the Intra Prediction, since the prediction process cannot start before the transforms and quantization loop finishes the reconstruction of the reference blocks. This work presents a low latency and high throughput architecture of the transforms and quantization loop, intending to reduce the impact of this loop in the Intra Prediction performance. The architecture was described in VHDL and synthesized to Altera Stratix II FPGA and to the TSMC 0.18μm CMOS technology. The architecture reaches an operation frequency of 129.3 MHz when mapped to standardcells, and takes 4 cycles to process an I4MB block, 24 cycles to process an I16MB block, and 22 cycles to process a chroma block. Those are the best results when compared with all related works considering the Intra Prediction constraints.