FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder
Journal of Signal Processing Systems
A rate-distortion optimization model for SVC inter-layer encoding and bitstream extraction
Journal of Visual Communication and Image Representation
Transforms and quantization design targeting the H.264/AVC intra prediction constraints
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Highly Efficient Transforms Module Solution for a H.264/SVC Encoder
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Overview of the Scalable Video Coding Extension of the H.264/AVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
Real-Time System for Adaptive Video Streaming Based on SVC
IEEE Transactions on Circuits and Systems for Video Technology
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The emergent standard H.264/SVC (scalable video coding) combines distinct complex techniques in order to allow efficient data compression considering data among consecutive layers. In practice, a complete implementation of this scalable encoder is not trivial, since the global complexity increases proportionally with the number of layers involved. Considering that, this paper proposes an innovative scalable architecture, which adopts a flexible approach able to reuse computational hardware modules in order to perform iteratively the SVC intra computational coding, for both the base layer and enhancement layers. In order to validate this proposal it was implemented in VHDL and compared with other conventional hardware approaches, confirming significant gain in terms of occupied memory and total chip area.