Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC intra prediction

Authors:
Daniel Palomino;Felipe Sampaio;Robson Dornelles;Luciano Agostini
Affiliations:
Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil;Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil;Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil;Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil
Venue:
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Year:
2009

Citing 3
Cited 0

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Abstract

This paper presents an efficient architectural design for a dedicated transforms and quantization loop. This design targeted the Intra Prediction of the H.264/AVC standard. The architecture was designed intending to achieve the best possible relation between throughput, latency and hardware resources consumption. The latency and throughput of this loop are extremely important to define the Intra Prediction performance. The use of hardware was reduced through the reuse of the same datapath for different calculations. The architecture was synthesized to Altera Stratix III FPGA and to the TSMC 0.18µm standard-cells technology. The architecture, when mapped to standard-cells, reaches a processing rate of 114 HDTV frames per second, attending the Intra Prediction restrictions.