Optimisation techniques for the system on chip implementation of JPEG encoder

  • Authors:

  • V. Amudha;B. Venkataramani;G. Seetharaman

  • Affiliations:

  • Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, India;Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, India;Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, India

  • Venue:
  • ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
  • Year:
  • 2005

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Abstract

Systems on chips have both general-purpose microprocessors and custom blocks optimized for specific functions. In this paper, Altera APEX 20KE200 based SOC kit with Nios soft-core processor is considered for the implementation of JPEG encoder. For an 8×8 matrix of image pixels, JPEG encoder is implemented in hardware as a custom block and its computation complexity is compared with that implemented using high level language. A number of optimization schemes are proposed for minimizing the computation time in the custom block. This includes employing the 13 multiplier Algorithm Architecture Transform (AAT) for 2D DCT computation, internal clock generation scheme which increases the speed of the custom instructions by 50% and use of memory read and write operations at different rates. A scheme for concurrent execution of the operations in the custom block and data transfer as well as other operations by the Nios core is also proposed. From the implementation results, it is observed that for sub image of size 8×8, the hardware custom block is faster by a factor of twenty six compared to software implementation. The optimization schemes proposed in this paper are also applicable for the computation of other image transforms such as 2D DWT and encoders such as ITU H.263.