Accelerated image processing on FPGAs

Authors:
B. A. Draper;J. R. Beveridge;A. P.W. Bohm;C. Ross;M. Chawathe
Affiliations:
Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA;-;-;-;-
Venue:
IEEE Transactions on Image Processing
Year:
2003

Citing 0
Cited 15

Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration

SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A real-time wavelet-domain video denoising implementation in FPGA

EURASIP Journal on Embedded Systems
Design and FPGA implementation of lifting scheme for 2D-DWT using wavepipelining

ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Optimisation techniques for the system on chip implementation of JPEG encoder

ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Design and evaluation of a hardware/software FPGA-based system for fast image processing

Microprocessors & Microsystems
Hardware-software system for acceleration of image processing operations

Machine Graphics & Vision International Journal
VLSI implementation of hybrid wave-pipelined 2D DWT using lifting scheme

VLSI Design
Architecture of an Integrated Software-Hardware System for Accelerated Image Processing

ICCVG 2008 Proceedings of the International Conference on Computer Vision and Graphics: Revised Papers
Implementation of the two-point angular correlation function on a high-performance reconfigurable computer

Scientific Programming
Real Time Hot Spot Detection Using FPGA

CIARP '09 Proceedings of the 14th Iberoamerican Conference on Pattern Recognition: Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications
Image processing with CNN in a FPGA-Based augmented reality system for visually impaired people

IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
FPGA implementation of the robust essential matrix estimation with RANSAC and the 8-point and the 5-point method

Facing the Multicore-Challenge II
Realizing real-time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware

Concurrency and Computation: Practice & Experience
VLSI architecture for real time edge detection of monochrome video sequences

Proceedings of the Eighth Indian Conference on Computer Vision, Graphics and Image Processing
Parallel rendering of human-computer interaction industrial applications on multi-/many-core platforms

HCI'13 Proceedings of the 15th international conference on Human-Computer Interaction: human-centred design approaches, methods, tools, and environments - Volume Part I

Quantified Score

Hi-index	0.01

Visualization

Abstract

The Cameron project has developed a language called single assignment C (SA-C), and a compiler for mapping image-based applications written in SA-C to field programmable gate arrays (FPGAs). The paper tests this technology by implementing several applications in SA-C and compiling them to an Annapolis Microsystems (AMS) WildStar board with a Xilinx XV2000E FPGA. The performance of these applications on the FPGA is compared to the performance of the same applications written in assembly code or C for an 800 MHz Pentium III. (Although no comparison across processors is perfect, these chips were the first of their respective classes fabricated at 0.18 microns, and are therefore of comparable ages.) We find that applications written in SA-C and compiled to FPGAs are between 8 and 800 times faster than the equivalent program run on the Pentium III.