Optimization theory with applications
Optimization theory with applications
Borg: A Knowledge-Based System for Automatic Generation of Image Processing Programs
IEEE Transactions on Pattern Analysis and Machine Intelligence
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Command Vector Memory Systems: High Performance at Low Cost
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A partitioning methodology that optimises the area on reconfigurable real-time embedded systems
EURASIP Journal on Applied Signal Processing
Accelerated image processing on FPGAs
IEEE Transactions on Image Processing
Aquarius: a dynamically reconfigurable computing platform
Proceedings of the 20th annual conference on Integrated circuits and systems design
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High parallelism degree is fundamental for high speed image processing systems. Modern FPGA devices can provide such parallelism plus flexibility. Temporal partitioning techniques can be used to implement large systems, splitting them into partitions (called contexts), multiplexed in a FPGA. This approach can increase the effective FPGA area, allowing high parallelism in the application tasks. However, the context reconfigurations can cause performance decrease. Intensive parallelism exploration of massive image data application compensates this overhead and can improve global performance. In this work, one reconfigurable computer platform and design space exploration techniques are proposed for mapping of image processing applications into FPGA slices. A library with different hardware implementation for different parallelism degree is used to better adjust space/time for each task. Experiments demonstrate the efficiency of the approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration.