A real-time edge detector: algorithm and VLSI architecture
Real-Time Imaging - Special issue on special-purpose architectures for real-time imaging, part 2
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
A Stereo Machine for Video-Rate Dense Depth Mapping and Its New Applications
CVPR '96 Proceedings of the 1996 Conference on Computer Vision and Pattern Recognition (CVPR '96)
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Evaluation of the Suitability of FPGAs for Embedded Vision Systems
CVPR '05 Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Workshops - Volume 03
Video-rate stereo depth measurement on programmable hardware
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
A Framework for Teaching Real-Time Digital Signal Processing With Field-Programmable Gate Arrays
IEEE Transactions on Education
Accelerated image processing on FPGAs
IEEE Transactions on Image Processing
An iterative logarithmic multiplier
Microprocessors & Microsystems
Design and hardware implementation of a stereo-matching system based on dynamic programming
Microprocessors & Microsystems
Decoding of Raptor codes on embedded systems
Microprocessors & Microsystems
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
Journal of Systems Architecture: the EUROMICRO Journal
Efficient and high performance FPGA-based rectification architecture for stereo vision
Microprocessors & Microsystems
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We evaluate the performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-processor and a host computer. A LabVIEW(TM) host application controlling a frame grabber and an industrial camera is used to capture and exchange video data with the hardware co-processor via a high speed USB2.0 channel, implemented with a standard macrocell. The FPGA accelerator is based on a Altera Cyclone II chip and is designed as a system-on-a-programmable-chip (SOPC) with the help of an embedded Nios II software processor. The SOPC system integrates the CPU, external and on chip memory, the communication channel and typical image filters appropriate for the evaluation of the system performance. Measured transfer rates over the communication channel and processing times for the implemented hardware/software logic are presented for various frame sizes. A comparison with other solutions is given and a range of applications is also discussed.