FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size

Authors:
F. Javier Toledo-Moreo;J. Javier MartíNez-Alvarez;Javier GarrigóS-Guerrero;J. Manuel FerráNdez-Vicente
Affiliations:
Dpto. Electrónica y Tecnología de Computadoras, Universidad Politécnica de Cartagena, Spain;Dpto. Electrónica y Tecnología de Computadoras, Universidad Politécnica de Cartagena, Spain;Dpto. Electrónica y Tecnología de Computadoras, Universidad Politécnica de Cartagena, Spain;Dpto. Electrónica y Tecnología de Computadoras, Universidad Politécnica de Cartagena, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2012

Citing 22
Cited 1

Machine vision

Machine vision
Reconfigurable pipelined 2-D convolvers for fast digital signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handbook of medical imaging

Handbook of medical imaging
Mapping of generalized template matching onto reconfigurable computers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A Novel 2D Filter Design Methodology for Heterogeneous Devices

FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing

DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels

Integration, the VLSI Journal
FPGA-based configurable systolic architecture for window-based image processing

EURASIP Journal on Applied Signal Processing
Hand-based Interface for Augmented Reality

FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A retinomorphic architecture based on discrete-time cellular neural networks using reconfigurable computing

Neurocomputing
Design and evaluation of a hardware/software FPGA-based system for fast image processing

Microprocessors & Microsystems
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Study of the contrast processing in the early visual system using a neuromorphic retinal architecture

Neurocomputing
Adaptive and optimal difference operators in image processing

Pattern Recognition
Digital Signal Processing with Field Programmable Gate Arrays

Digital Signal Processing with Field Programmable Gate Arrays
Feature Extraction & Image Processing, Second Edition

Feature Extraction & Image Processing, Second Edition
A Massively Parallel Coprocessor for Convolutional Neural Networks

ASAP '09 Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

IEEE Transactions on Computers
Run-time self-reconfigurable 2D convolver for adaptive image processing

Microelectronics Journal
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays

Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Bridging the GPGPU-FPGA efficiency gap

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A Comparison of FPGA and GPU for Real-Time Phase-Based Optical Flow, Stereo, and Local Image Features

IEEE Transactions on Computers

A practical evaluation of the performance of the Impulse CoDeveloper HLS tool for implementing large-kernel 2-D filters

Journal of Real-Time Image Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the FPGA-based implementation of 2-D convolution with medium-large kernels. It is a multiplierless solution based on Distributed Arithmetic implemented using general purpose resources in FPGAs. Our proposal is modular and coefficient independent, so it remains fully flexible and customizable for any application. The architecture design includes a control unit to manage efficiently the operations at the borders of the input array. Results in terms of occupied resources and timing are reported for different configurations. We compare these results with other approaches in the state of the art to validate our approach.