Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems
The Journal of Supercomputing
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A Multiplierless 2-D Convolver Chip for Real-Time Image Processing
Journal of VLSI Signal Processing Systems
An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
An efficient star acquisition method based on SVM with mixtures of kernels
Pattern Recognition Letters
Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution
Microprocessors & Microsystems
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels
Integration, the VLSI Journal
FPGA-based configurable systolic architecture for window-based image processing
EURASIP Journal on Applied Signal Processing
A reconfigurable computing framework for multi-scale cellular image processing
Microprocessors & Microsystems
Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Run-time self-reconfigurable 2D convolver for adaptive image processing
Microelectronics Journal
A Comparison Study for a Neural Network Based Embedded Appliance
Proceedings of the 2011 conference on Neural Nets WIRN10: Proceedings of the 20th Italian Workshop on Neural Nets
Design of an efficient multiplier-less architecture for multi-dimensional convolution
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
Journal of Systems Architecture: the EUROMICRO Journal
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Reconfigurable Constant Multiplier for FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Optimizing image processing on multi-core CPUs with Intel parallel programming technologies
Multimedia Tools and Applications
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In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated. However, the proposed concept is not limited to a particular processor.