Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital Image Processing Methods
Digital Image Processing Methods
Digital Video: An introduction to MPEG-2
Digital Video: An introduction to MPEG-2
Digital Image Processing
Architectures for generalized 2D FIR filtering using separable filter structures
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
A two-level interleaving architecture for serial convolvers
IEEE Transactions on Signal Processing
Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution
Microprocessors & Microsystems
Subthreshold FIR Filter Architecture for Ultra Low Power Applications
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
System Comparison of Electronic and Optical Correlator
Journal of Signal Processing Systems
Design of an efficient multiplier-less architecture for multi-dimensional convolution
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper proposes a new real-time 2-D convolver chip with no multiplier. Several commercial 2-D convolver chips have many multipliers and existing multiplierless architectures have many shift-and-accumulators to meet the real-time image processing requirement, i.e., the standard of CCIR601. Even though the proposed architecture uses only one shift-and-accumulator, it can meet the real-time requirement. Furthermore, because it controls the input data sequence, the proposed chip does not require row buffers to store two adjacent rows as do commercial chips, and it can further reduce the gate count. The proposed architecture can reduce the gate count by more than 70 and 90% compared to HSP48901 and HSP48908, respectively, and the gate count of the computation block itself by more than 70% compared to existing multiplierless architectures. We have implemented the chip using the Samsung™ 0.8 μm SOG cell library (KG60K). The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement. The proposed architecture is especially suitable for larger size convolutions because of its small gate count.