An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels

Authors:
Ming Z. Zhang;Hau T. Ngo;Adam R. Livingston;Vijayan K. Asari
Affiliations:
Old Dominion University;Old Dominion University;Old Dominion University;Old Dominion University
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

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Abstract

A high performance digital architecture for computing 2-D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy to identify the pixels to be fed to different processing elements helps reducing the data storage requirements in the circuitry. The new design results in 75% reduction in multipliers and 50% reduction in adders when compared with the conventional systolic architecture. The proposed architecture design is capable of performing convolution operations with 14脳14 kernel at a rate of 57 1024脳1024 frames per second in a Xilinxýs Virtex 2v2000ff896-4 FPGA.