Design of an efficient flexible architecture for color image enhancement

Authors:
Ming Z. Zhang;Li Tao;Ming-Jung Seow;Vijayan K. Asari
Affiliations:
Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA;Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA;Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA;Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

A novel architecture for performing digital color image enhancement based on reflectance/illumination model is proposed in this paper. The approach promotes the log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the approximation techniques for efficient estimation of log2 and inverse-log2. A new quadrant symmetric architecture is also incorporated into the design of homomorphic filter to achieve very high throughput rate which is part of V component enhancement in Hue-Saturation-Value (HSV) color space. The pipelined design of the filter features the flexibility in reloading a wide range of kernels for different frequency responses. A generalized architecture of max/min filter is also presented for efficient extraction of V component. With effective color space conversion, the HSV-domain image enhancement architecture is able to achieve a throughput rate of 182.65 million outputs per second (MOPS) or equivalently 52.8 billion operations per second on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 182.65 MHz. It can process over 174.2 mega-pixel (1024×1024) frames per second and consumes approximately 70.7% less hardware resource when compared to the design presented in [10].