One-Dimensional Digital Signal Processing
One-Dimensional Digital Signal Processing
Multidimensional Digital Signal Processing
Multidimensional Digital Signal Processing
Digital Systems: Hardware Organization and Design
Digital Systems: Hardware Organization and Design
Structure of Computers and Computations
Structure of Computers and Computations
The FDP, a Fast Programmable Signal Processor
IEEE Transactions on Computers
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations
IEEE Transactions on Computers
Design of a Massively Parallel Processor
IEEE Transactions on Computers
Computer
A kernel-independent, pipelined architecture for real-time 2-D convolution
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution
Microprocessors & Microsystems
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels
Integration, the VLSI Journal
Block Data Processing Using Commercial Processors
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Parallel image processing with the block data parallel architecture
IBM Journal of Research and Development
Design of an efficient multiplier-less architecture for multi-dimensional convolution
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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In this paper, a generic computational primitive is developed for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. This computational primitive can form the basis for a single chip processor for one-dimensional and two-dimensional digital signal processing. A multiprocessor architecture for real-time implementation of spatial domain filters is developed with each processing unit in the network implementing the computational primitive. This multiprocessor system has a simple control scheme, a simple interconnection network, a very high efficiency, and low data transfers and storage requirements. Thus, it avoids the bottlenecks associated with traditional parallel computers and multiprocessor systems.