Design of a high performance architecture for real-time enhancement of video stream captured in extremely low lighting environment

Authors:
Hau T. Ngo;Ming Zhang;Li Tao;Vijayan K. Asari
Affiliations:
Department of Electrical and Computer Engineering, United States Naval Academy, Annapolis, MD, United States;Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA, United States;Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA, United States;Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA, United States
Venue:
Microprocessors & Microsystems
Year:
2009

Citing 5
Cited 2

A new FPGA/DSP-based parallel architecture for real-time image processing

Real-Time Imaging
An FPGA-Based Architecture for Real Time Image Feature Extraction

ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 1 - Volume 01
An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A multiscale retinex for bridging the gap between color images and the human observation of scenes

IEEE Transactions on Image Processing
A pipelined architecture for real-time correction of barrel distortion in wide-angle camera images

IEEE Transactions on Circuits and Systems for Video Technology

An iterative logarithmic multiplier

Microprocessors & Microsystems
Real-time video surveillance on an embedded, programmable platform

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A high performance digital architecture for the implementation of a non-linear image enhancement technique is proposed in this paper. The image enhancement is based on a luminance dependent non-linear enhancement algorithm which achieves simultaneous dynamic range compression, colour consistency and lightness rendition. The algorithm provides better colour fidelity, enhances less noise, prevents the unwanted luminance drop at the uniform luminance areas, keeps the 'bright' background unaffected, and enhances the 'dark' objects in 'bright' background. The algorithm contains a large number of complex computations and thus it requires specialized hardware implementation for real-time applications. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Estimation techniques are also utilized in the hardware algorithmic design to achieve faster, simpler and more efficient architecture. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 67 Mega-pixels (Mpixels) per second.