VLSI array processors
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
Parallel computer vision
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
The connection machine
Connection autonomy in SIMD computers: a VLSI implementation
Journal of Parallel and Distributed Computing
The GIOTTO system: a parallel computer for image processing
Real-Time Imaging - Special issue on special-purpose architectures for real-time imaging, part 2
Advanced Computer Architectures
Advanced Computer Architectures
The cytocomputer: A practical pipelined image processor
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Parallel programmable video co-processor design
ICIP '95 Proceedings of the 1995 International Conference on Image Processing (Vol. 1)-Volume 1 - Volume 1
Hardware Design of Shape-Preserving Contour Tracing for Object of Segmented Images
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
Domain-Specific codesign for automated visual inspection systems
IbPRIA'05 Proceedings of the Second Iberian conference on Pattern Recognition and Image Analysis - Volume Part I
Efficient video denoising based on dynamic nonlocal means
Image and Vision Computing
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In this article, we present a new reconfigurable parallel architecture oriented to video-rate computer vision applications. This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors Pij. These processors are interconnected by means of a systolic 2D array of FPGA-based video-addressing units which allow video-rate links between any two processors in the net to overcome the associated restrictions in classic crossbar systems such as those which occur with butterfly connections. This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. This proposed open architecture allows the host to deal with final high-level interpretation tasks. The exchange of information between the linked processors Pij of the 2D net lies in the transfer of complete images, pixel by pixel, at video-rate. Therefore, any kind of processor satisfying such a requirement can be integrated. Furthermore, the whole architecture has been designed host-independent.