Boundary detection using mathematical morphology
Pattern Recognition Letters
Digital circuit design using FPGAs
CIE '96 Proceedings of the 19th international conference on Computers and industrial engineering
Implementation of mathematical morphological operations for spatial data processing
Computers & Geosciences
Digital Image Processing
An FPGA Architecture for High Speed Edge and Corner Detection
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Real Time Noise Cleaning of Ultrasound Images
CBMS '04 Proceedings of the 17th IEEE Symposium on Computer-Based Medical Systems
A clocking technique for FPGA pipelined designs
Journal of Systems Architecture: the EUROMICRO Journal
Adaptive mathematical morphology for edge linking
Information Sciences—Informatics and Computer Science: An International Journal
FPGA architecture for fast parallel computation of co-occurrence matrices
Microprocessors & Microsystems
Robust shape-preserving contour tracing with synchronous redundancy pruning
Pattern Recognition Letters
Designing mathematical morphology algorithms on FPGAs: an application to image processing
CAIP'05 Proceedings of the 11th international conference on Computer Analysis of Images and Patterns
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A hardware design of shape-preserving contour tracing for objects in a segmented image for robot vision and pattern recognition applications is presented in this paper. The proposed contour tracing consists of two processes, namely progressive boundary linking (PBL) and synchronous redundancy pruning (SRP). The proposed method is realized on a System on Chip (SoC) with open-source processor IP core, LEON3, utilizing AMBA bus. Implementation results show that the proposed design achieves better results in terms of accuracy and hardware efficiency comparing with other existing boundary extraction methods such as morphological boundary extraction.