Hardware Design of Shape-Preserving Contour Tracing for Object of Segmented Images
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
Feature extraction using reconfigurable hardware
ICCVG'10 Proceedings of the 2010 international conference on Computer vision and graphics: Part II
VLSI architecture for real time edge detection of monochrome video sequences
Proceedings of the Eighth Indian Conference on Computer Vision, Graphics and Image Processing
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This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.