Communications of the ACM
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Digital Design: Principles and Practices
Digital Design: Principles and Practices
Art of Digital Design: An Introduction to Top-Down Design
Art of Digital Design: An Introduction to Top-Down Design
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A doubly-latched asynchronous pipeline
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Optimizing CMOS Implementations of the C-element
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Practical Design and Performance Evaluation of Completion Detection Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
High-frequency pulse width modulation implementation using FPGA and CPLD ICs
Journal of Systems Architecture: the EUROMICRO Journal
Hardware Design of Shape-Preserving Contour Tracing for Object of Segmented Images
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
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This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits.